1. Field of the Invention
The present invention relates to a method of fabricating a metal oxide semiconductor (MOS) device and, more particularly, to a method of fabricating an MOS device that includes a self-aligned silicide (salicide) structure.
2. Discussion of Related Art
Process steps of a conventional method of fabricating an MOS device that includes a salicide structure are described immediately below with reference to the idealized cross-sectional views of FIGS. 1A-1F.
As shown in FIG. 1A, a thin, insulating thermal oxide film 102a is grown on the surface of a lightly-doped silicon substrate 101 of a first conductivity type and a doped polysilicon layer 103a is formed on the thin oxide film. After a first photoresist coating has been spun onto the polysilicon layer, the photoresist coating is patterned by means of conventional exposure and development process steps to form a photoresist pattern 104.
Masked by the photoresist pattern 104, the doped polysilicon layer 103a is etched in order to form regularly-spaced, parallel, doped polysilicon gate electrode strips 103, as shown in FIG. 1B. (Each polysilicon gate electrode consists of multiple single-crystal silicon regions, which are called grains or crystallites, separated by grain boundaries. Although the as-deposited polysilicon of the gate electrodes may be amorphous, it subsequently becomes polycrystalline as a consequence of post-deposition processing at elevated temperatures.)
After the photoresist pattern 104 has been removed, a low dose of low energy dopants of a second conductivity type is implanted into the substrate, which is masked by the gate electrodes 103, and then electrically activated by means of a thermal process in order to form shallow, lightly-doped source/drain regions 105 within the substrate to either side of each of the gate electrodes 103. (Alternatively, the photoresist pattern may be removed after, rather than before, the implantation has been performed.) Lightly-doped source/drain regions 105 are thus self-aligned to each of the gate electrodes 103.
As shown in FIG. 1C, an oxide layer is deposited over the surface of the substrate and then etched back to form oxide sidewall spacers 106 contiguous to either side of each of the gate electrodes 103. To facilitate the description below, a gate electrode structure is defined to consist of a gate electrode 103 and the sidewall spacers 106 contiguous to that electrode.
As shown in FIG. 1D, a higher dose of energetic dopants of the second conductivity type is implanted into the substrate, which is masked by the gate electrode structures, and then electrically activated by means of a thermal process in order to form heavily-doped source/drain regions 107 within the substrate to either side of each of the gate electrode structures. (Alternatively and more economically, dopants that will comprise both the lightly-and heavily-doped source/drain regions may be electrically activated at the same time by means of a single thermal process after the later implantation.) Heavily-doped source/drain regions 107 are thus self-aligned to each of the gate electrode structures and extend further beneath the surface of the substrate than do the lightly-doped source/drain regions 105. Additional grain boundaries 108 are generated in the polysilicon gate electrodes 103 during implantation of the dopants that will comprise the source/drain regions.
As shown in FIG. 1E, heavy ions of the second conductivity type (typically As.sup.- for a lightly-doped p-type substrate or BF.sub.2.sup.+ for a lightly-doped n-type substrate) are implanted into the substrate and the gate electrodes in order to form amorphous layers 109 adjacent to the surface of the single-crystal silicon substrate above each of the heavily-doped source/drain regions 107 and adjacent to the upper surface of each of the polysilicon gate electrodes 103. (Adjacent may or may not imply contact, but always implies the absence of anything of the same kind in between.) Amorphization with heavy ions reduces channeling effects and thus facilitates the formation of shallow silicide layers at the surfaces of the single-crystal silicon substrate and the polysilicon gate electrodes. The energetic heavy ions of a conventional amorphization process can easily pass through the grain boundaries of the polysilicon gate electrodes.
As shown in FIG. 1F, a metal layer (typically consisting of titanium) is deposited over the upper surface of the substrate, which is masked by the gate electrode structures, and then annealed. Silicon of the amorphized regions 109 of the polysilicon gate electrodes 103 and the single-crystal silicon substrate reacts with the deposited metal to form silicide layers 111 of uniform electrical and mechanical properties at the surface of each of the gate electrodes 103 and at the surface of the substrate above each of the heavily-doped source/drain regions 107. The silicides thus formed at the surface of the single-crystal silicon substrate are refefred to a salicide structure, since they are self-aligned to the gate electrode structures and are formed at the same time as the polycides (i.e., polycrystalline silicides) at the surface of each of the gate electrodes. Unreacted metal, deposited, for example, on the insulating gate sidewall spacers, is removed by means of a selective etch that does not attack the silicides, the gate sidewall spacers, or the substrate.
As was noted above, the energetic ions employed in a conventional amorphization process readily pass through the grain boundaries of the polycrystalline gate electrodes into the channel regions of the substrate beneath the gate electrodes. Regions of nonuniform dopant concentration 110 are thereby generated at random within the channel regions of the substrate, which cause unpredictable (and thus unwanted) variations in the threshold voltage of the MOS transistors being fabricated.